Semiconductor devices and methods of manufacturing the same

ABSTRACT

A semiconductor device includes a substrate including cell and dummy regions, first channel structures on the cell region and extending in a first direction vertical with respect to the substrate, gate lines surrounding outer sidewalls of the first channel structures and extending in a second direction parallel to the substrate, the gate lines being spaced apart from each other along the first direction, cutting lines between the gate lines on the cell region and extending in the second direction, dummy patterns spaced apart from each other along the first direction on the dummy region, the dummy patterns having a stepped shape along a third direction parallel to the top surface of the substrate and perpendicular to the second direction, at least a portion of the dummy patterns including a same conductive material as that in the gate lines, and dummy lines through the dummy patterns.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. Non-Provisional application claims priority under 35 USC §119to U.S. Provisional Application No. 62/130,868, filed on Mar. 10, 2015in the USPTO.

Korean Patent Application Nos. 10-2015-0033128, filed on Mar. 10, 2015,and 10-2015-0068931, filed on May 18, 2015, in the Korean IntellectualProperty Office, and entitled: “Semiconductor Devices and Methods ofManufacturing the Same,” are incorporated by reference herein in itsentirety.

BACKGROUND

1. Field

Example embodiments relate to semiconductor devices and methods ofmanufacturing the same. More particularly, example embodiments relate tosemiconductor devices including vertical channels and methods ofmanufacturing the same.

2. Description of the Related Art

Recently, a vertical memory device including a plurality of memory cellsstacked vertically from a surface of a substrate has been developed. Inthe vertical memory device, a high stress may be imposed on verticallystacked layers because the memory cells may be repeatedly stackedvertically. Thus, structural and/or electrical defects may be caused inthe vertical memory device.

SUMMARY

Example embodiments provide a semiconductor device having improvedstructural and electrical reliability.

According to example embodiments, a semiconductor device includes asubstrate, first channel structures, gate lines, cutting lines, dummypatterns and dummy lines. The substrate may include a cell region and adummy region. The first channel structures may be disposed on the cellregion of the substrate. The first channel structures may extend in afirst direction vertical to a top surface of the substrate. The gatelines may surround outer sidewalls of the first channel structures andextend in a second direction parallel to the top surface of thesubstrate. The gate lines may be spaced apart from each other along thefirst direction. The cutting lines may be interposed between the gatelines on the cell region. The cutting lines may extend in the seconddirection. The dummy patterns may be spaced apart from each other alongthe first direction on the dummy region. The dummy patterns may have astepped shape along a third direction parallel to the top surface of thesubstrate and perpendicular to the second direction. At least a portionof the dummy patterns may include a conductive material the same as thatincluded in the gate lines. The dummy lines may extend through the dummypatterns.

In example embodiments, the dummy region may be adjacent to an endportion of the cell region in the third direction.

In example embodiments, the dummy lines may include a conductivematerial the same as that included in the cutting lines.

In example embodiments, the dummy lines may extend in the thirddirection.

In example embodiments, a distance between the dummy lines may be equalto or greater than a distance between the cutting lines.

In example embodiments, at least one of the dummy patterns may includeconductive patterns spaced apart in the second direction, and asacrificial pattern interposed between the conductive patterns. Theconductive patterns may include the conductive material the same as thatof the gate lines, and the sacrificial pattern may include a nitride.

In example embodiments, the dummy lines may extend in a fourth directiondiagonal to the second direction.

In example embodiments, the dummy lines may extend in the seconddirection.

In example embodiments, at least a portion of the dummy patterns mayinclude the conductive material the same as that of the gate lines, anda remaining portion of the dummy patterns may include a conductivepattern and a sacrificial pattern. The conductive pattern may includethe conductive material and the sacrificial pattern may include anitride.

In example embodiments, the dummy patterns may be positioned atcorresponding levels of the gate lines.

In example embodiments, the semiconductor device may further includeinsulating interlayer patterns between the dummy patterns neighboring inthe first direction and between the gate lines neighboring in the firstdirection.

In example embodiments, the cutting lines may serve as common sourcelines, and the dummy lines may serve as dummy source lines.

In example embodiments, each of the dummy lines may have a uniform widthor include different widths.

In example embodiments, the semiconductor device may further include athird channel structure extending through the dummy patterns on thedummy region of the substrate.

In example embodiments, the semiconductor device may further include adummy cell on a portion of the cell region adjacent to the dummy region.

According to other example embodiments, a semiconductor device includesa substrate, first channel structures, gate lines, first insulatinginterlayer patterns, cutting lines, dummy patterns, second insulatinginterlayer patterns, dummy lines. The substrate may include a cellregion and a dummy region. The first channel structures may be disposedon the cell region of the substrate. The first channel structures mayextend in a first direction vertical to a top surface of the substrate.The gate lines may surround outer sidewalls of the first channelstructures and extend in a second direction parallel to the top surfaceof the substrate. The gate lines may be spaced apart from each otheralong the first direction. The first insulating interlayer patterns maybe interposed between the gate lines neighboring in the first direction.The cutting lines may be interposed between the gate lines on the cellregion. The cutting lines may extend in the second direction. The dummypatterns may be spaced apart from each other along the first directionon the dummy region. The dummy patterns may have a stepped shape along athird direction parallel to the top surface of the substrate andperpendicular to the second direction. At least a portion of the dummypatterns may include a conductive material the same as that included inthe gate lines. The second insulating interlayer patterns may beinterposed between the dummy patterns neighboring in the firstdirection. The dummy lines may extend through the dummy patterns and thesecond insulating interlayer patterns.

According to yet other example embodiments, a semiconductor deviceincludes a substrate including a cell region and a dummy region, firstchannel structures on the cell region of the substrate, the firstchannel structures extending in a first direction vertical with respectto a top surface of the substrate, gate lines surrounding outersidewalls of the first channel structures and extending in a seconddirection parallel to the top surface of the substrate, the gate linesbeing spaced apart from each other along the first direction, commonsource lines between the gate lines on the cell region, the commonsource lines extending in the second direction, dummy patterns spacedapart from each other along the first direction on the dummy region, thedummy patterns having a stepped shape along a third direction parallelto the top surface of the substrate and perpendicular to the seconddirection, at least a portion of the dummy patterns including a sameconductive material as that included in the gate lines, and dummy sourcelines extending through the dummy patterns and having a differentconfiguration than the common source lines in top view.

The dummy source lines may extend in a different direction than thecommon source lines, as viewed in top view.

A distance between neighboring dummy source lines may be greater than adistance between neighboring common source lines.

The dummy source lines and the common source lines may include a sameconductive material.

The dummy source lines may include a plurality of dummy source linesegments spaced apart from each other in the second and thirddirections.

BRIEF DESCRIPTION OF THE DRAWINGS

Features will become apparent to those of ordinary skill in the art bydescribing in detail exemplary embodiments with reference to theattached drawings, in which:

FIGS. 1 to 4 illustrate a top plan view, a perspective view andcross-sectional views of a semiconductor device in accordance withexample embodiments;

FIGS. 5 to 13 illustrate cross-sectional views and top plan views of amethod of manufacturing a semiconductor device in accordance withexample embodiments;

FIGS. 14 and 15 illustrate a top plan view and a perspective view,respectively, of a semiconductor device in accordance with exampleembodiments;

FIGS. 16 and 17 illustrate top plan views of a method of manufacturing asemiconductor device in accordance with example embodiments;

FIGS. 18 and 19 illustrate a top plan view and a perspective view,respectively, of a semiconductor device in accordance with exampleembodiments;

FIGS. 20, 21 and 22 illustrate a top plan view, a perspective view, anda cross-sectional view, respectively, illustrating a semiconductordevice in accordance with example embodiments;

FIGS. 23 and 24 illustrate cross-sectional views of a method ofmanufacturing a semiconductor device in accordance with exampleembodiments;

FIGS. 25, 26 and 27 illustrate a top plan view, a perspective view, anda cross-sectional view, respectively, of a semiconductor device inaccordance with example embodiments;

FIG. 28 illustrates a top plan view of a semiconductor device inaccordance with example embodiments;

FIG. 29 illustrates a top plan view of a semiconductor device inaccordance with example embodiments;

FIG. 30 illustrates a top plan view of a semiconductor device inaccordance with example embodiments; and

FIG. 31 illustrates a top plan view of a semiconductor device inaccordance with example embodiments.

DETAILED DESCRIPTION

Various example embodiments will be described more fully hereinafterwith reference to the accompanying drawings, in which some exampleembodiments are shown. Example embodiments may, however, be embodied inmany different forms and should not be construed as limited to those setforth herein. Rather, these example embodiments are provided so thatthis description will be thorough and complete, and will fully conveythe scope of the exemplary implementations to those skilled in the art.In the drawings, the sizes and relative sizes of layers and regions maybe exaggerated for clarity.

It will be understood that when an element or layer is referred to asbeing “on,” “connected to” or “coupled to” another element or layer, itcan be directly on, connected or coupled to the other element or layeror intervening elements or layers may be present. In contrast, when anelement is referred to as being “directly on,” “directly connected to”or “directly coupled to” another element or layer, there are nointervening elements or layers present. Like numerals refer to likeelements throughout. As used herein, the term “and/or” includes any andall combinations of one or more of the associated listed items.

It will be understood that, although the terms first, second, third,fourth etc. may be used herein to describe various elements, components,regions, layers and/or sections, these elements, components, regions,layers and/or sections should not be limited by these terms. These termsare only used to distinguish one element, component, region, layer orsection from another region, layer or section. Thus, a first element,component, region, layer or section discussed below could be termed asecond element, component, region, layer or section without departingfrom the teachings of the example embodiments.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the exemplary term “below” can encompass both anorientation of above and below. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particularexample embodiments only and is not intended to be limiting. As usedherein, the singular forms “a,” “an” and “the” are intended to includethe plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

Example embodiments are described herein with reference tocross-sectional illustrations that are schematic illustrations ofidealized example embodiments (and intermediate structures). As such,variations from the shapes of the illustrations as a result, forexample, of manufacturing techniques and/or tolerances, are to beexpected. Thus, example embodiments should not be construed as limitedto the particular shapes of regions illustrated herein but are toinclude deviations in shapes that result, for example, frommanufacturing. For example, an implanted region illustrated as arectangle will, typically, have rounded or curved features and/or agradient of implant concentration at its edges rather than a binarychange from implanted to non-implanted region. Likewise, a buried regionformed by implantation may result in some implantation in the regionbetween the buried region and the surface through which the implantationtakes place. Thus, the regions illustrated in the figures are schematicin nature and their shapes are not intended to illustrate the actualshape of a region of a device and are not intended to limit.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof skill in the art. It will be further understood that terms, such asthose defined in commonly used dictionaries, should be interpreted ashaving a meaning that is consistent with their meaning in the context ofthe relevant art and will not be interpreted in an idealized or overlyformal sense unless expressly so defined herein.

Although corresponding plan views and/or perspective views of somecross-sectional view(s) may not be shown, the cross-sectional view(s) ofdevice structures illustrated herein provide support for a plurality ofdevice structures that extend along two different directions as would beillustrated in a plan view, and/or in three different directions aswould be illustrated in a perspective view. The two different directionsmay or may not be orthogonal to each other. The three differentdirections may include a third direction that may be orthogonal to thetwo different directions. The plurality of device structures may beintegrated in a same electronic device. For example, when a devicestructure (e.g., a memory cell structure or a transistor structure) isillustrated in a cross-sectional view, an electronic device may includea plurality of the device structures (e.g., memory cell structures ortransistor structures), as would be illustrated by a plan view of theelectronic device. The plurality of device structures may be arranged inan array and/or in a two-dimensional pattern.

FIGS. 1 to 4 are a top plan view, a perspective view, andcross-sectional views illustrating a semiconductor device in accordancewith example embodiments. Specifically, FIG. 2 is an enlargedperspective view of a portion “A” in FIG. 1. FIGS. 3 and 4 arecross-sectional views taken along lines I-I′ and II-II' in FIG. 1,respectively.

In example embodiments, the semiconductor device may be a non-volatilevertical memory device. Memory cells included in the semiconductordevice may be formed on a channel extending vertically, e.g., along anormal direction, with respect to a top surface of a substrate.

A direction substantially vertical to the top surface of the substrateis referred to as a first direction, and two directions substantiallyparallel to the top surface of the substrate and substantially crossingeach other are referred to as a second direction and a third direction.For example, the second direction and the third direction aresubstantially perpendicular to each other. Additionally, a directionindicated by an arrow and a reverse direction thereof are considered asa same direction. The above mentioned definitions of the directions arethe same throughout all the figures in this specification.

Referring to FIGS. 1 to 4, a semiconductor device may include a memorycell structure disposed on a cell region of a substrate 100, and a dummystructure disposed on a dummy region of the substrate 100. For example,the dummy region of the substrate 100 may be located at both ends of thecell region in the third direction.

The substrate 100 may include a semiconductor material, e.g., silicon(Si) or germanium (Ge).

The memory cell structure may include first and second channelstructures 120 a and 120 b, gate lines 134, and a common source line(CSL) 144. The gate lines 134 may be formed on outer sidewalls of thefirst and second channel structures 120 a and 120 b. The gate lines 134may extend in the second direction, and may be spaced apart from eachother along the first direction. The CSL 144 may extend through the gatelines 134, and may extend in the second direction. The CSL 144 may serveas a cutting line intersecting the gate lines 134.

The first and second channel structures 120 a and 120 b may each includea semiconductor pattern 110, a channel layer 114 extending from a topsurface of the semiconductor pattern 110 in the first direction, adielectric layer structure 112 surrounding an outer sidewall of thechannel layer 114, a filling pattern 116 in the channel layer 114, and apad 118 disposed on the dielectric layer 112, the channel layer 114, andthe filling pattern 116.

The semiconductor pattern 110 may include a semiconductor material,e.g., silicon or germanium. In some embodiments, the semiconductorpattern 110 may be omitted, and the channel layer 114 may be formed,e.g., directly, on the substrate 100.

The channel layer 114 may protrude vertically from a top surface of thesubstrate 100, and may have a hollow, e.g., cylindrical, shape or, e.g.,a cup, shape. In an embodiment, the channel layer 114 may have, e.g., asolid cylindrical shape or a pillar shape. The channel layer 114 mayinclude, e.g., polysilicon or single crystalline silicon. P-typeimpurities, e.g., boron (B), may be doped in a portion of the channellayer 114.

The dielectric layer structure 112 may be formed on the outer sidewallof the channel layer 114, and may have a substantial straw shape, e.g.,the dielectric layer structure 112 may have a shape of a cylindricalshell surrounding the channel layer 114. In some embodiments, thedielectric layer structure 112 may include a tunnel insulation layer, acharge storage layer, and a blocking layer sequentially formed from theouter sidewall of the channel layer 114. For example, the dielectriclayer structure 112 may have an oxide-nitride-oxide (ONO) layeredstructure.

The filling pattern 116 may include an insulation material, e.g.,silicon oxide. If the channel layer 114 has a solid cylindrical shape ora pillar shape, the filling pattern 116 may be omitted.

Upper portions of the dielectric layer structure 112, the channel layer114, and the filling pattern 116 may be capped or closed by the pad 118.The pad 118 may include, e.g., polysilicon or single crystallinesilicon, and may further include, e.g., n-type impurities, e.g.,phosphorous (P) or arsenic (As).

In example embodiments, the first channel structures 120 a may bearranged along the second direction to form a channel column, e.g., aplurality of the first channel structures 120 a may be arranged in anarray along the second direction. A plurality of the channel columns maybe arranged along the third direction, e.g., the channel columns may bespaced apart from each other along the third direction with the CSL 144therebetween.

The gate lines 134 may surround the first channel structure 120 a andmay extend in the second direction. In example embodiments, the gatelines 134 may surround the plurality of the channel columns arrangedalong the third direction.

The gate lines 134 may include a metal having a low electricalresistance or a nitride thereof. For example, the gate line 134 mayinclude tungsten (W), tungsten nitride, titanium (Ti), titanium nitride,tantalum (Ta), tantalum nitride, platinum (Pt), or the like.

In example embodiments, a lowermost gate line of the gate lines 134 mayserve as a ground selection line (GSL), and an uppermost gate line ofthe gate lines 134 may serve as a string selection line (SSL). The gatelines 134 between the GSL and the SSL may serve as word lines. Thenumber of levels of the GSL, the word lines, and the SSL may be properlyadjusted in consideration of a circuit design and a degree ofintegration of the semiconductor device.

An insulating interlayer pattern 102 a may be interposed at each levelbetween the gate lines 134. The insulating interlayer pattern 102 a mayinclude, e.g., a silicon oxide-based material.

The insulating interlayer patterns 102 a and the gate lines 134 may bealternately stacked along the first direction such that a firststructure 138 may be defined. The first structure 138 may extend in thesecond direction. Both lateral portions of the first structure 138 inthe second direction may serve as a wiring region and have a steppedshape. Thus, different wirings may be connected to different gate lines134 included in the first structure 138 so that an electrical signal maybe individually applied to each gate line 134.

A central portion of the first structure 138 which may not have thestepped shape may serve as a main cell region, and the lateral portionhaving the stepped shape may serve as the wiring region. The wirings mayinclude contact plugs 150 that may be in contact with gate lines 134,and conductive lines electrically connected to the contact plugs 150.

The first channel structure 120 a may be disposed on the main cellregion, and may be provided as a portion of a memory cell. The secondchannel structure 120 b may be disposed on the wiring region, and maynot be provided as the portion of the memory cell. The second channelstructure 120 b may serve as a supporting pillar for the lateral portionof the first structure 138.

A plurality of the second channel structures 120 b may not be in contactwith the wirings, or may be spaced apart from the wirings. The secondchannel structures 120 b may have an arrangement different from that ofthe first channel structures 120 a. In example embodiments, a density ina unit area of the second channel structures 120 b may be less than thatof the first channel structures 120 a.

A first opening 122 may be formed between the first structures 138neighboring each other. The first opening 122 may extend in the seconddirection. The first opening 122 may extend through the alternatingstack of insulating interlayer patterns 102 a and the gate lines 134 tothe top surface of the substrate 100. An insulation pattern 142 may beformed on a sidewall of the first opening 122 (FIG. 3). The gate lines134 and the CSL 144 may be insulated from each other by the insulationpattern 142. An impurity region 126 may be formed at an upper portion ofthe substrate 100 which may be exposed through the first opening 122.

The CSL 144 may be in the first opening 122 and may be in contact withthe impurity region 126. The CSL 144 may extend in the second direction.The CSL 144 may include a metal having a low resistance, e.g., W, Ti,Ta, Pt, etc., or a nitride thereof.

The dummy structure disposed on the dummy region may include a secondstructure 140 and a dummy source line 146. A plurality of the secondstructures 140 may be arranged and spaced apart from each other alongthe second direction. A plurality of the dummy source lines 146 mayextend between the neighboring second structures 140.

The second structure 140 may include the insulating interlayer patterns102 a and dummy patterns 136 which may be alternately stacked. Thesecond structure 140 may extend in a direction that may be differentfrom the second direction, e.g., the second structure 140 may extend inthe third direction.

The insulating interlayer pattern 102 a included in the second structure140 may be the same as the insulating interlayer pattern 102 a of thefirst structure 138. The dummy patterns 136 included in the secondstructure 140 may be formed at levels corresponding to the gate lines134 of the first structure 138.

At least a portion of the dummy patterns 136 may include the sameconductive material as that of the gate lines 134. In exampleembodiments, a width in the second direction of the second structure 140may be substantially the same as a width in the third direction of thefirst structure 138. The second structure 140 may have a steppedstructure along the third direction.

A second opening 124 may be formed between neighboring second structures140. The second opening 124 may extend in a direction different from thesecond direction. The second opening 124 may extend to the top surfaceof the substrate 100. In example embodiments, the second opening 124 mayextend in the third direction, and a plurality of the second openings124 may be formed to be spaced apart from each other along the seconddirection. In example embodiments, a width in the second direction ofthe second opening 124 may be equal to or greater than a width in thethird direction of the first opening 122.

An impurity region may be formed at an upper portion of the substrate100 exposed through the second opening 124. The impurity region underthe second opening 124 may be formed together with the impurity region126 under the first opening 122 of the cell region. However, theimpurity region under the second opening 124 may not participate in anyelectrical operation.

The insulation pattern 142 may be formed on a sidewall of the secondopening 124. The dummy pattern 136 and the dummy source line 146 may beinsulated from each other by the insulation pattern 142.

The dummy source line 146 may be disposed in the second opening 124, andmay be in contact with the top surface of the substrate 100. The dummysource line 146 may extend in the third direction. The dummy source line146 may include a conductive material substantially the same as that ofthe CSL 144.

A third channel structure 120 c having a construction substantially thesame as that of the first channel structure 120 a may be disposed on thedummy region. The third channel structure 120 c may not serve as achannel of the memory cell, and may merely serve as a supporting pillarof the second structure 140. A plurality of the third channel structures120 c may be provided in an arrangement different from those of thefirst channel structures 120 a and/or the second channel structures 120b. In example embodiments, a density in a unit area of the third channelstructures 120 c may be less than that of the first channel structures120 a.

In example embodiments, memory cells defined at both ends in the thirddirection on the cell region may be dummy cells 148 that may notparticipate in an actual operation. Thus, wirings for applying a signalmay not be connected to the dummy cells 148.

As the degree of integration of the semiconductor device becomes higher,the stacked number of the gate lines 134 and the insulating interlayerpatterns 102 a may also become greater. Thus, aspect ratios of the firstand second structures 138 and 140 may be increased. Accordingly, abending or a collapse of the first and second structures 138 and 140 maybe caused due to a stress imposed thereon. For example, the secondstructure 140 and end portions of the first structure 138 may be morevulnerable to the bending or the collapse because shrinkage and releaseof the structures may be irregularly repeated by the stress.

However, according to example embodiments, the first opening 122 and thesecond opening 124 may extend in different direction, and thus stressorientations imposed on the first and second structures 138 and 140 maybe different. Therefore, a stress imposed on the first structure 138while forming the first opening 122 may be reduced.

At least a portion of the dummy patterns 136 may include the sameconductive material as that of the gate lines 134. The dummy patterns136 may not include a nitride that may be a significant source ofstress, or a portion including the nitride may be reduced. Thus, thestress imposed on the first structure 138 may be reduced. Therefore, thebending or the collapse of the first and second structures 138 and 140may be suppressed.

FIGS. 5 to 13 are cross-sectional views and top plan views illustratingstages in a method of manufacturing a semiconductor device in accordancewith example embodiments. For example, FIGS. 5 to 7, 9, 11 and 13 arecross-sectional views illustrating stages in a method of manufacturingthe semiconductor device of FIGS. 1 to 4. FIGS. 8, 10 and 12 areenlarged top plan views illustrating the stages in the method.Specifically, FIGS. 5 to 7, 9, 11 and 13 are taken along the line I-I′indicated in FIG. 1.

Referring to FIG. 5, the insulating interlayers 102 and the sacrificiallayers 104 may be alternately and repeatedly formed on the substrate100, which includes a cell region and a dummy region. The insulatinginterlayers 102 and the sacrificial layers 104 may be partially removedto form a mold structure 106. End portion of the mold structure 106 inthe second and third directions may have stepped structures. The dummyregion may be adjacent to an end portion of the cell region in the thirddirection.

In example embodiments, the insulating interlayer 102 may be formed ofan oxide-based material, e.g., silicon dioxide, silicon oxycarbideand/or silicon oxyfluoride. The sacrificial layer 104 may be formed of amaterial that may have an etching selectivity with respect to theinsulating interlayer 102 and may be easily removed by a wet etchingprocess. For example, the sacrificial layer 104 may be formed of anitride-based material, e.g., silicon nitride and/or siliconboronitride.

The sacrificial layers 104 may be removed by a subsequent process toprovide spaces for gate lines. Thus, the number of the insulatinginterlayers 102 and the sacrificial layers 104 may be determined inconsideration of the number of the gate lines.

For example, a photoresist pattern may be formed on an uppermostinsulating interlayer 102 such that end portions of the uppermostinsulating interlayer 102 may be exposed. End portions of the insulatinginterlayers 102 and the sacrificial layers 104 may be etched using thephotoresist pattern as an etching mask. End portions of the photoresistpattern may then be removed so that a width of the photoresist patternmay be reduced. Next, the insulating interlayers 102 and the sacrificiallayers 104 may be etched using the photoresist pattern as the etchingmask again. Etching processes may be repeated in a similar manner asdescribed above to obtain the mold structure 106.

A portion of the mold structure 106 on the dummy region may have astepped structure along the third direction. A portion of the moldstructure 106 on the cell region may include stepped structures at bothend portions in the second direction.

Referring to FIG. 6, a lower insulation layer 108 covering lateralportions of the mold structure 106 may be formed on the substrate 100.First, second and third channel structures may be formed through themold structure 106 and the lower insulation layer 108

In example embodiments, an insulation layer covering the mold structure106 may be formed on the substrate 100. The insulation layer may beformed of, e.g. silicon oxide by a chemical vapor deposition (CVD)process, a spin coating process, etc. An upper portion of the insulationlayer may be planarized by a chemical mechanical polish (CMP) processand/or an etch-back process until the uppermost insulating interlayer102 is exposed to form the lower insulation layer 108. The lowerinsulation layer 108 may cover the stepped structures at the endportions of the mold structure 106. In example embodiments, the lowerinsulation layer 108 may include an insulation material substantiallythe same as or similar to that of the insulating interlayer 102.

The mold structure 106 and/or the lower insulation layers 108 may bepartially etched along the first direction to form the first to thirdchannel holes. For example, a hard mask may be formed on the uppermostinsulating interlayer 102 and the lower insulation layer 108. The moldstructure 106 and the lower insulation layer 108 may be partiallyremoved by, e.g., a dry etching process through the hard mask to formthe first to third channel holes.

The first and second channel holes may be formed through the moldstructure 106 on the cell region, and the third channel hole may beformed through the mold structure on the dummy region. In exampleembodiments, a plurality of the first channel holes may be formedthrough a central portion of the mold structure 106 (e.g., on a maincell region) that may not have the stepped structure. The first channelholes may be formed along the second and third directions regularly. Thesecond channel holes may be formed through the stepped structure in thesecond direction of the mold structure 106 (e.g., on a wiring region).

In example embodiments, the second channel holes may be formed in anarrangement different from that of the first channel holes. In exampleembodiments, the third channel holes may be formed in an arrangementdifferent from those of the first channel holes and/or the secondchannel holes.

Each of the second and third channel holes may have a size the same asor different from that of the first channel hole. The second and thirdchannel holes formed at the end portions of the mold structure 106 maynot extend to the substrate 100 due to an etching loading to cause anot-open defect. In some embodiments, the size of the second channelhole and/or the third channel hole may be increased relatively to thesize of the first channel hole so that the not-open defect may beavoided.

A silicon epitaxial growth process may be performed from the substrate100 exposed through the first to third channel holes so thatsemiconductor patterns 110 may be formed at lower portions of the firstto third channel holes. In some embodiments, the formation of thesemiconductor pattern 110 may be omitted.

A dielectric layer may be formed along sidewalls and bottoms of thefirst to third channel holes, the uppermost insulating interlayer 102and the lower insulation layer 108. In example embodiments, thedielectric layer may be formed by sequentially forming a blocking layer,a charge storage layer and a tunnel insulation layer. For example, theblocking layer may be formed using an oxide, e.g., silicon oxide, thecharge storage layer may be formed using silicon nitride or a metaloxide, and the tunnel insulation layer may be formed using an oxide,e.g., silicon oxide. In example embodiments, the dielectric layer may beformed as an oxide-nitride-oxide (ONO) layered structure. The blockinglayer, the charge storage layer, and the tunnel insulation layer may beformed by a CVD process, a plasma-enhanced chemical vapor deposition(PECVD) process, an atomic layer deposition (ALD) process, etc.

Portions of the dielectric layer formed on the bottoms of the first tothird channel holes may be removed by, e.g., an etch-back process sothat a top surface of the semiconductor pattern 110 may be exposed.Thus, the dielectric layer structure 112 may be formed on each sidewallof the first to third channel holes. The dielectric layer structure 112may have a substantial straw shape.

The channel layer 114 may be formed conformally on the uppermostinsulating interlayer 102, the dielectric layer structure 112, and thesemiconductor pattern 110, and the filling pattern 116 filling remainingportions of the first to third channel holes may be formed. In exampleembodiments, the channel layer 114 may be formed of polysilicon oramorphous silicon optionally doped with impurities. In some embodiments,the channel layer 114 may sufficiently fill the first to third channelholes. In this case, the formation of the filling pattern 116 may beomitted.

Upper portions of the dielectric layer structure 112, the channel layer114, and the filling pattern 116 may be removed by an etch-back processto form recesses. A pad layer sufficiently filling the recesses may beformed on the uppermost insulating interlayer 102 and the lowerinsulation layer 108. An upper portion of the pad layer may beplanarized until top surfaces of the uppermost insulating interlayer 102and/or the lower layer 108 may be exposed to form pads 118 fromremaining portions of the pad layer. In example embodiments, the padlayer may be formed using, e.g., polysilicon optionally doped withn-type impurities. The planarization process may include a CMP processand/or an etch-back process.

After performing the aforementioned processes, the first channelstructure 120 a, the second channel structure 120 b, and the thirdchannel structure (also see FIG. 1) may be formed in the first channelhole, the second channel hole, and the third channel hole, respectively.In example embodiments, the plurality of the first channel structures120 a may be formed through the mold structure 106 on the main cellregion, the plurality of the second channel structures 120 b may beformed through the mold structure 106 on the wiring region, and theplurality of the third channel structures 120 c may be formed throughthe mold structure 106 on the dummy region.

The first to third channel structures 120 a, 120 b, and 120 c may havesubstantially the same construction, while only the first channelstructures 120 a are illustrated in FIG. 6. The first channel structures120 a may substantially serve as a portion of the memory cells. Thesecond and third channel structures 120 b and 120 c may serve as pillarssupporting both portions of the mold structure 106.

Referring to FIGS. 7 and 8, the mold structure 106 and the lowerinsulation layer 108 may be anisotropically etched to form the firstopenings 122 on the cell region, and the second openings 124 on thedummy region. The top surface of the substrate 100 may be exposedthrough bottoms of the first and second openings 122 and 124.

As illustrated in FIG. 8, the first openings 122 may extend in thesecond direction. The mold structure 106 may be cut or intersected bythe first openings 122 along the second direction to form first moldstructures 128 spaced apart from each other along the third direction.The first mold structure 128 may surround the plurality of the firstchannel structures 120 a, and extend in the second direction.

The second openings 124 may extend in a direction different from thesecond direction, e.g., the second opening 124 may extend in the thirddirection (FIG. 8). The mold structure 106 may be cut or intersected bythe second openings 124 along the third direction to form second moldstructures 130 spaced apart from each other along the second direction.

In example embodiments, a width in the third direction of the firstopening 122 may be substantially the same as a width in the seconddirection of the second opening 124. In example embodiments, a distancebetween the first openings 122 neighboring in the third direction may besubstantially the same as a distance between the second openings 124neighboring in the second direction. For example, a width in the seconddirection of the second mold structure 130 may be substantially the sameas a width in the third direction of the first mold structure 128.

The first and second mold structures 128 and 130 may include insulatinginterlayer patterns 102 a and sacrificial patterns 104 a alternatelystacked. Both ends of the first mold structure 128 in the seconddirection may have stepped structures in the second direction. Thesecond mold structure 130 may include a stepped structure in the thirddirection.

Etching directions and/or extending directions of the first and secondopenings 122 and 124 may be different so that a stress generated duringthe etching process for forming the first mold structures 128 may bereduced or mitigated. Thus, defects, e.g., bending of the first moldstructure 128, may be avoided.

Impurities may be implanted through the first and second openings 122and 124 to form impurity regions 126. The impurities may be n-typeimpurities, e.g., P or As.

Referring to FIGS. 9 and 10, the sacrificial patterns 104 a exposedthrough the first and second openings 122 and 124 may be removed to formfirst gaps 132 a and second gaps 132 b. In example embodiments, thesacrificial patterns 104 a may be removed by a wet etching processusing, e.g., phosphoric acid and/or sulfuric acid as an etchantsolution.

In example embodiments, the sacrificial patterns 104 a formed on thecell region may be fully removed. The sacrificial patterns 104 a formedon the dummy region may be fully or partially removed. For example, ifthe distance between the first openings 122 neighboring in the thirddirection is substantially the same as the distance between the secondopenings 124 neighboring in the second direction, the sacrificialpatterns 104 a formed on the dummy region may be fully removed.

The first gaps 132 a may be formed at spaces from which the sacrificialpatterns 104 a of the cell region are removed. The second gaps 132 b maybe formed at spaces from which the sacrificial patterns 104 a of thedummy region may be removed. Sidewalls of the first channel structures120 a may be partially exposed by the first gap 132 a.

Referring to FIGS. 11 and 12, gate lines 134 may be formed in the firstgaps 132 a, and dummy patterns 136 may be formed in the second gaps 132b. In example embodiments, a gate electrode layer sufficiently fillingthe first and second gaps 132 a and 132 b may be formed. The gateelectrode layer may also partially fill the first and second openings122 and 124, and may be also formed on upper surfaces of the first andsecond mold structure 128 and 130.

The gate electrode layer may be formed using a metal or a metal nitridehaving low electrical resistance and work function. For example, thegate electrode layer may be formed of tungsten, tungsten nitride,titanium, titanium nitride, tantalum, tantalum nitride, platinum, etc.In an embodiment, the gate electrode layer may be formed as amulti-layered structure including a barrier layer formed of a metalnitride, and a metal layer.

Portions of the gate electrode layer formed in the first and secondopenings 122 and 124, and formed on the upper surfaces of the first andsecond mold structures 128 and 130 may be removed. Accordingly, the gateline 134 may be formed in the first gap 132 a at each level, and thedummy pattern 136 may be formed in the second gap 132 b at each level.

After performing the aforementioned processes, a first structure 138including the insulating interlayer patterns 102 a and the gate lines134, and extending in the second direction may be formed on the cellregion. Both end portions in the second direction of the first structure138 may have a stepped structure. The second structure 140 including theinsulating interlayer patterns 102 a and the dummy patterns 136, andextending in the third direction may be formed on the dummy region.

As described above, the sacrificial patterns 104 a included in thesecond mold structure 130 may be replaced with the dummy patterns 136.Thus, the second structure 140 may not include the sacrificial patterns104 a formed of a nitride generating a stress. Therefore, a stresstransferred to the first structure 138 may be reduced so that astructural stability of the first structure 138 may be improved.

Referring to FIG. 13, the insulation patterns 142 may be formed onsidewalls of the first and second openings 122 and 124. The CSL 144 andthe dummy source line 146 filling the first opening 122 and the secondopening 124, respectively, may be formed.

In example embodiments, an insulation layer may be formed conformally onsidewalls and bottoms of the first and second openings 122 and 124, andon upper surfaces of the first structure 138, the second structure 140,and the lower insulation layer 108. Portions of the insulation layerformed on the bottoms of the first and second openings 122 and 124, andon the upper surfaces of the first and second structures 138 and 140 maybe removed by, e.g., an anisotropic etching process. Thus, theinsulation pattern 142 may be formed on each sidewall of the first andsecond openings 122 and 124.

A conductive layer filling the first and second openings 122 and 124 maybe formed on the insulation pattern 142. The conductive layer may beplanarized until the upper surfaces of the first and second structures138 and the lower insulation layer 108 may be exposed to form the CSL144 and the dummy source line 146. The planarization process may includea CMP process and/or an etch-back process.

In some embodiments, an upper insulation layer may be formed on thefirst and second structures 138 and 140 and the lower insulation layer108. The upper insulation layer may be etched to form contact holesthrough which the gate lines 134 may be exposed on the wiring region.Contact plugs 150 may be formed in the contact holes. Wiringselectrically connected to the contact plugs 150 may be further formed onthe upper insulation layer. Thus, a memory cell structure may be formedon the cell region, and a dummy structure may be formed on the dummyregion.

Memory cells defined at both ends in the third direction on the cellregion may serve as the dummy cells 148 that may not participate in anactual operation. Thus, wirings and contact plugs for applying a signalmay not be connected to the dummy cells 148.

FIGS. 14 and 15 are a top plan view and a perspective view,respectively, illustrating a semiconductor device in accordance withexample embodiments. FIG. 15 illustrates a second structure of thesemiconductor device of FIG. 14.

The semiconductor device of FIGS. 14 and 15 may have elements and/orconstructions substantially the same as or similar to those illustratedwith reference to FIGS. 1 to 4 except for a dummy structure on a dummyregion. Thus, detailed descriptions of repeated elements and/orstructures are omitted herein, and like reference numerals are used todesignate like elements.

Referring to FIGS. 14 and 15, the dummy structure on the dummy regionmay include second structures 140 a spaced apart from each other alongthe second direction, and a dummy source line 146 a extending betweenthe second structures 140 a. A width in the second direction of thesecond structure 140 a may be greater than a width in the thirddirection of the first structure 138 on the cell region.

The second structure 140 a may include the insulating interlayerpatterns 102 a and dummy patterns 163 which may be alternately stacked.The second structure 140 a may extend in a direction different from thesecond direction. In example embodiments, the second structure 140 a mayextend in the third direction.

The insulating interlayer pattern 102 a included in the second structure140 a may include substantially the same material as that of theinsulating interlayer pattern 102 a included in the first structure 138.The insulating interlayer patterns 102 a of the first and secondstructures 138 and 140 a may be positioned at a same height at eachlevel.

The dummy pattern 163 of the second structure 140 a may be positioned ata same height as that of a gate line 134 of the first structure 138 ateach level. The dummy pattern 163 at each level may include conductivepatterns 160 at both end portions in the second direction, and a secondsacrificial pattern 162 interposed between the conductive patterns 160.The conductive pattern 160 may include substantially the same conductivematerial as that of the gate line 134. The second sacrificial pattern162 may include a nitride-based material such as silicon nitride orsilicon boronitride. The second sacrificial pattern 162 may remain fromnot being replaced with the conductive material.

The second structure 140 a may have a stepped structure along the thirddirection. For example, lengths in the third direction of the insulatinginterlayer patterns 102 a and the dummy patterns 163 may be reduced inthe first direction from a top surface of the substrate 100.

A second opening 124 a may be formed between the second structures 140a. The second opening 124 a may extend in a direction different from thesecond direction. In example embodiments, the second opening 124 a mayextend in the third direction, and a plurality of the second openings124 a may be formed along the second direction. The second opening 124 amay extend through a lower insulation layer (not illustrated) to the topsurface of the substrate 100.

An insulation pattern may be formed on a sidewall of the second opening124 a. The dummy pattern 163 and a dummy source line 146 a may beinsulated from each other by the insulation pattern. The dummy sourceline 146 a may be disposed in the second opening 124 a, and may be incontact with the top surface of the substrate 100. The dummy source line146 a may extend in the third direction. The dummy source line 146 a mayinclude substantially the same conductive material as that of the CSL144 of the cell region. A distance between the dummy source lines 146 aneighboring in the second direction may be greater than a distancebetween the CSLs 144 neighboring in the third direction.

Third channel structures 120 c that may have a constructionsubstantially the same as that of the first channel structures 120 a onthe cell region, and may be disposed on the dummy region. The thirdchannel structure 120 c may merely serve as a pillar for supporting thesecond structure 140 a.

In example embodiments, an amount of the nitride-based material such assilicon nitride may be reduced in the second structure 140 a. Therefore,stress-related defects may be avoided in the semiconductor device.

FIGS. 16 and 17 are top plan views illustrating a method ofmanufacturing a semiconductor device in accordance with exampleembodiments. For example, FIGS. 16 and 17 illustrate a method ofmanufacturing the semiconductor device of FIGS. 14 and 15. FIGS. 16 and17 illustrate an end portion in the third direction of a cell region,and a dummy region.

Processes substantially the same as or similar to those illustrated withreference to FIGS. 5 and 6 may be performed to form a mold structure 106on a substrate, and first to third channel structures 120 a, 120 b and120 c extending through the mold structure 106. A lower insulation layer108 covering stepped portions of the mold structure 106 may be formed.

Referring to FIG. 16, the mold structure 106 and the lower insulationlayer 108 may be partially removed by, e.g., an anisotropic etchingprocess, to form the first openings 122 and the second openings 124 a onthe cell region and the dummy region, respectively. The top surface ofthe substrate may be exposed through the first and second openings 122and 124 a.

The first opening 122 may have a construction substantially the same asthat illustrated with reference to FIG. 7. The second opening 124 a mayextend in a direction different from that of the first opening 122. Inexample embodiments, the second opening 124 a may extend in the thirddirection. A distance between the second openings 124 a neighboring inthe second direction may be greater than a distance between the firstopenings 122 neighboring in the third direction.

The mold structure 106 may be cut or intersected by the first opening122 along the second direction such that first mold structures 128 maybe formed. The first mold structure 128 may surround a plurality ofchannel columns, and may extend in the second direction.

The mold structure 106 may be cut or intersected by the second openings124 a along the third direction such that second mold structures 130 amay be formed. A width in the second direction of the second moldstructure 130 a may be greater than a width in the third direction ofthe first mold structure 128.

The first and second mold structures 128 and 130 a may includeinsulating interlayer patterns and sacrificial patterns that may bealternately stacked. Impurities may be implanted through the first andsecond openings 122 and 124 a to form impurity regions at upper portionsof the substrate.

Referring to FIG. 17, the sacrificial patterns exposed by the first andsecond openings 122 and 124 a may be removed by, e.g., an isotropicetching process. The sacrificial patterns formed on the cell region maybe fully removed. Thus, first gaps 132 a may be formed at spaces fromwhich the sacrificial patterns on the cell region are removed. Asidewall of the first channel structure 120 a may be partially exposedby the first gap 132 a.

The sacrificial pattern on the dummy region may have a width greaterthan that of the sacrificial pattern on the cell region. Thus, thesacrificial pattern on the dummy region may be only partially removedwhile the sacrificial pattern on the cell region may be fully removed.Accordingly, second gaps 168 b may be formed at spaces from which thesacrificial patterns on the dummy region are removed, and a secondsacrificial pattern 162 having a reduced width may remain at each level.A sidewall of the second sacrificial pattern 162 may be exposed by thesecond gap 168 b.

Referring to FIGS. 14 and 15 again, the gate line 134 may be formed ineach first gap 132 a, and the conductive pattern 160 may be formed ineach second gap 168 b. The gate line 134 and the conductive pattern 160may be formed by processes substantially the same as or similar to thoseillustrated with reference to FIGS. 11 and 12.

After performing the aforementioned processes, the first structure 138extending in the second direction and including the insulatinginterlayer patterns and gate lines 134 may be formed on the cell region.The second structure 140 a extending in the third direction andincluding the insulating interlayer patterns 102 a and dummy patterns163 may be formed on the dummy region.

As described above, a portion of the sacrificial pattern included in thesecond mold structure 130 a may be replaced with the conductive patternto form the second structure 140 a. Thus, stress imposed on the firststructure 138 may be reduced to suppress structural defects of the firststructure 138. Subsequently, insulation patterns may be formed onsidewalls of the first and second openings 122 and 124 a, and then theCSL 144 and the dummy source line 146 a may be formed in the firstopening 122 and the second opening 124 a, respectively, as illustratedwith reference to FIG. 13 to obtain the semiconductor device of FIG. 14.

FIGS. 18 and 19 are a top plan view and a perspective view,respectively, illustrating a semiconductor device in accordance withexample embodiments. FIG. 19 is an enlarged perspective view of aportion “A” in FIG. 18.

The semiconductor device of FIGS. 18 and 19 may have elements and/orconstructions substantially the same as or similar to those illustratedwith reference to FIGS. 1 to 4, except for a dummy structure on a dummyregion. Thus, detailed descriptions of repeated elements and/orstructures are omitted herein, and like reference numerals are used todesignate like elements.

Referring to FIGS. 18 and 19, the dummy structure on the dummy regionmay include second structures 140 b spaced apart from each other on thesubstrate 100 along the second direction, and a dummy source line 146 bextending between the second structures 140 b. The second structure 140b may include insulating interlayer patterns 102 a and dummy patterns163 a that may be alternately stacked.

The dummy pattern 163 a may include substantially the same material asthat of the gate line 134 on the cell region. In some embodiments, thedummy pattern 163 a may include a conductive pattern (not illustrated)formed of the same conductive material as that of the gate line 134, anda second sacrificial pattern (not illustrated) including siliconnitride.

In example embodiments, a width in the second direction of the secondstructure 140 b may be substantially the same as a width in the thirddirection of the first structure 138. In some embodiments, the width inthe second direction of the second structure 140 b may be greater thanthe width in the third direction of the first structure 138.

The second structure 140 b may extend in a direction different from thesecond direction. In example embodiments, the second structure 140 b mayextend in a fourth direction diagonal to the second and thirddirections. Thus, a second opening 124 b between the second structures140 b may extend in the fourth direction.

An insulation pattern may be formed on a sidewall of the second opening124 b. The dummy source line 146 b may be formed in the second opening124 b. The dummy source line 146 b may extend in the fourth direction.The semiconductor device of FIGS. 18 and 19 may be manufactured by amethod substantially the same as or similar to that illustrated withreference to FIGS. 5 to 13, except that the second opening 124 b may beformed to extend in the fourth direction.

FIGS. 20, 21 and 22 are a top plan view, a perspective view, and across-sectional view, respectively, illustrating a semiconductor devicein accordance with example embodiments. FIG. 21 is an enlargedperspective view of a portion “A” in FIG. 20. FIG. 22 is across-sectional view taken along line of FIG. 20. For convenience ofdescriptions, an illustration of a third channel structure is omitted inFIG. 21.

The semiconductor device of FIGS. 20 to 22 may have elements and/orconstructions substantially the same as or similar to those illustratedwith reference to FIGS. 1 to 4, except for a dummy structure on a dummyregion. Thus, detailed descriptions of repeated elements and/orstructures are omitted herein, and like reference numerals are used todesignate like elements.

Referring to FIGS. 20 to 22, the dummy structure on the dummy region mayinclude a second structure 170 having a stepped structure along thethird direction, and a second opening 172 extending through the secondstructure 170 and in the second direction, and a dummy source line 176formed in the second opening 172.

The second structure 170 may include the insulating interlayer patterns102 a and dummy patterns 174 that may be alternately stacked. An endportion in the third direction of the second structure 170 may have astepped shape. The second structure 170 may be cut or intersected alongthe second direction by the second opening 172.

The second opening 172 may have a trench shape extending in the seconddirection, and a plurality of the second openings 172 may be arrangedalong the second and the third directions. In example embodiments, thesecond openings 172 may have different lengths in the second direction.In example embodiments, a distance between the second openings 172neighboring in the second direction may not be uniform. In someembodiments, the second openings 172 may have the same length in thesecond direction, and a distance between the second openings 172neighboring in the second direction may be uniform.

The dummy source line 176 may be disposed in the second opening 172. Aninsulation pattern 142 may be formed on a sidewall of the second opening172. The dummy source line 176 may extend in the same direction as thatof the CSL 144 on the cell region.

The dummy source line 176 may extend in the second direction, and theplurality of the dummy source lines 176 may be spaced apart from eachother in the second direction. The dummy source lines 176 may be furtherarranged along the third direction. A length in the second direction ofthe dummy source line 176 may be less than that of the CSL 144. Inexample embodiments, a distance between the dummy source lines 176neighboring in the third direction may be equal to or greater than adistance between the CSLs 144 neighboring in the third direction.

The dummy pattern 174 may include the same material as that of a gateline 134 of the cell region. In some embodiments, the dummy pattern 174may include a conductive pattern formed of the same material as that ofthe gate line 134, and a second sacrificial pattern 104 a formed ofsilicon nitride.

In example embodiments, memory cells defined at both ends in the thirddirection on a cell region may serve as dummy cells 148 that may notparticipate in an actual operation. Thus, wirings and contact plugs forapplying a signal may not be connected to the dummy cells 148.

In some embodiments, the CSL included in the dummy cell 148 may have ashape substantially the same as those of the CSL 144 on a main cellregion and/or the dummy source line 176.

FIGS. 23 and 24 are cross-sectional views illustrating a method ofmanufacturing a semiconductor device in accordance with exampleembodiments. For example, FIGS. 23 and 24 illustrate a method ofmanufacturing the semiconductor device of FIGS. 20 to 22.

Referring to FIG. 23, processes substantially the same as or similar tothose illustrated with reference to FIGS. 5 and 6 may be performed toform a mold structure 106 on the substrate 100, and first to thirdchannel structures 120 a, 120 b, and 120 c extending through the moldstructure 106. The lower insulation layer 108 covering stepped portionsof the mold structure 106 may be formed.

The mold structure 106 and the lower insulation layer 108 may bepartially removed by, e.g., an anisotropic etching process, to form thefirst openings 122 and the second openings 172 on the cell region andthe dummy region, respectively. The top surface of the substrate 100 maybe exposed through the first and second openings 122 and 172.

The first opening 122 may have a shape or a structure substantially thesame as that illustrated with reference to FIG. 7. The second opening172 may have a trench shape extending in the second direction, and aplurality of the second openings 172 may be spaced apart from each otheralong the second direction. The second openings 172 may be also formedalong the third directions. In example embodiments, the first and secondopenings 122 and 172 may extend in the same direction.

In example embodiments, a distance between the second openings 172neighboring in the third direction may be substantially the same as adistance between the first openings 122 neighboring in the thirddirection. In some embodiments, the distance between the second openings172 neighboring in the third direction may be greater than the distancebetween the first openings 122 neighboring in the third direction.

Referring to FIG. 24, processes substantially the same as or similar tothose illustrated with reference to FIGS. 9 and 10 may be performed toremove the sacrificial patterns 104 a from the mold structure 106.

The sacrificial patterns 104 a formed on the cell region may be fullyremoved. While removing the sacrificial patterns 104 a on the cellregion, the sacrificial patterns formed on the dummy region may be fullyor partially removed. In example embodiments, a portion of thesacrificial pattern 104 a may remain at an area in which the sacrificialpattern 104 a may not be exposed by the second opening 172.

First gaps 132 a may be formed at spaces from which the sacrificialpatterns 104 a on the cell region are removed, and second gaps 178 maybe formed at spaces from which the sacrificial patterns 104 a on thedummy region are removed. A sidewall of the first channel structure 120a may be partially exposed by the first gap 132 a.

Referring to FIGS. 20 to 22 again, the gate line 134 may be formed inthe first gap 132 a at each level, and the dummy pattern 174 may beformed in the second gap 178 at each level. The gate line 134 and thedummy pattern 174 may be formed by processes substantially the same asor similar to those illustrated with reference to FIGS. 11 and 12.

Subsequently, the insulation patterns 142 may be formed on sidewalls ofthe first and second openings 122 and 172, and the CSL 144 and a dummysource line 176 filling the first opening 122 and the second opening172, respectively, may be formed as illustrated with reference to FIG.13. Thus, the semiconductor device of FIGS. 20 to 22 may be achieved.

FIGS. 25, 26, and 27 are a top plan view, a perspective view, and across-sectional view, respectively, illustrating a semiconductor devicein accordance with example embodiments. The semiconductor device ofFIGS. 25 to 27 may have elements and/or constructions substantially thesame as or similar to those illustrated with reference to FIGS. 1 to 4,except for a dummy structure on a dummy region. Thus, detaileddescriptions of repeated elements and/or structures are omitted herein,and like reference numerals are used to designate like elements.

Referring to FIGS. 25 to 27, the dummy structure on the dummy region mayinclude a second structure 170 a having a stepped structure along thethird direction, a second opening 172 a extending through the secondstructure 170 a and in the second direction, and a dummy source line 176a formed in the second opening 172 a. The second structure 170 a mayinclude insulating interlayer patterns 102 a and dummy patterns 174 athat may be alternately stacked.

The second opening 172 a may extend in the second direction. In someembodiments, a plurality of the second openings 172 a may be formedalong the third direction. In example embodiments, the first opening 122and the second opening 172 a may have substantially the same shape.

The dummy source line 176 a may be formed in the second opening 172 a.The insulation pattern 142 may be formed on a sidewall of the secondopening 172 a.

The dummy source line 176 a may extend in a direction substantially thesame as that of the CSL 144 on the cell region. For example, the dummysource line 176 a and the CSL may extend in the second direction. Thesecond structure 170 a may be cut or intersected by the dummy sourceline 176 a. In example embodiments, a width in the third direction ofthe dummy source line 176 a may be equal to or greater than that of theCSL 144.

In example embodiments, a distance between the dummy source lines 176 amay be greater than a distance between the CSLs 144 neighboring in thethird direction. FIG. 25 only illustrates one dummy source line 176 a oneach dummy region, however, at least two dummy source lines 176 a may beformed on the each dummy region.

The dummy pattern 174 a may include the same material as that of a gateline 134. In example embodiments, the dummy pattern 174 a at a certainlevel may include a conductive pattern 160 a formed of the same materialas that of the gate line 134, and a second sacrificial pattern 162 aformed of a nitride. The dummy pattern 174 a at a certain level may onlyinclude the conductive pattern 160 a.

In example embodiments, memory cells defined at both ends in the thirddirection on the cell region may serve as dummy cells 148 that may notparticipate in an actual operation. Thus, wirings and contact plugs forapplying a signal may not be connected to the dummy cells 148.

In example embodiments, the CSL included in the dummy cell 148 may havea shape substantially the same as that of the CSL 144 on a main cellregion. In some embodiments, the CSL included in the dummy cell 148 mayhave a shape substantially the same as that of the dummy source line 176a.

The semiconductor device of FIGS. 25 to 27 may be manufactured from amethod substantially the same as or similar to that illustrated withreference to FIGS. 23 and 24. However, when forming the first and secondopenings, the second openings may be formed to cut the second structurealong the second direction and have a greater distance therebetween thana distance between the first openings.

FIG. 28 is a top plan view illustrating a semiconductor device inaccordance with example embodiments.

The semiconductor device of FIG. 28 may have elements and/orconstructions substantially the same as or similar to those illustratedwith reference to FIGS. 1 to 4 except for a dummy structure on a dummyregion. Thus, detailed descriptions on repeated elements and/orstructures are omitted herein, and like reference numerals are used todesignate like elements

Referring to FIG. 28, the dummy structure on the dummy region mayinclude a second structure 170 b having a stepped structure along thethird direction, a second opening 172 b extending through the secondstructure 170 b and in the second direction, and a dummy source line 176b formed in the second opening 172 b.

The second structure 170 b may include insulating interlayer patternsand dummy patterns that may be alternately stacked.

The second opening 172 b may extend in the second direction, and aplurality of the second openings 172 b may be formed along the thirddirection. The second opening 172 b may have different widths therein.The second structure 172 b may be cut or intersected by the secondopening 172 b.

The dummy source line 176 b may be disposed in the second opening 172 b.An insulation pattern may be formed on a sidewall of the second opening172 b.

The dummy source line 176 b may extend in the same direction as that ofthe CSL 144 on a cell region. The dummy source line 176 b may havedifferent widths according to a shape of the second opening 172 b.

In example embodiments, the dummy source line 176 b may have a shape inwhich a portion of a first width W1 and a portion of a second width W2smaller than the first width W1 may be repeated.

The dummy pattern may include the same material as that of a gate lineon the cell region. In some embodiments, the dummy pattern at a certainlevel may include a conductive pattern formed of the same material asthat of the gate line, and a second sacrificial pattern formed of anitride. The dummy pattern at a certain level may only include theconductive pattern.

The semiconductor device of FIG. 28 may be manufactured by a methodsubstantially the same as or similar to that illustrated with referenceto FIGS. 23 and 24 except that the second opening 172 b may be formed tohave different widths.

FIG. 29 is a top plan view illustrating a semiconductor device inaccordance with example embodiments.

The semiconductor device of FIG. 29 may have elements and/orconstructions substantially the same as or similar to those illustratedwith reference to FIGS. 1 to 4 except for a dummy structure on a dummyregion. Thus, detailed descriptions on repeated elements and/orstructures are omitted herein, and like reference numerals are used todesignate like elements.

Referring to FIG. 29, the dummy structure on the dummy region mayinclude a second structure 170 c having a stepped structure along thethird direction, a second opening 172 c extending through the secondstructure 170 c and in the second direction, and a dummy source line 176c formed in the second opening 172 c.

The second structure 170 c may include insulating interlayer patternsand dummy patterns that may be alternately stacked.

The second opening 172 c may extend in the second direction, and aplurality of the second openings 172 c may be formed along the thirddirection. The second opening 172 c may have a width equal to or greaterthan that of a first opening 122.

The dummy source line 176 c may be disposed in the second opening 172 c.An insulation pattern may be formed on a sidewall of the second opening172 c.

The dummy source line 176 c may have a width in the third directionequal to or greater than that of the CSL 144 on a cell region. At leasta portion of the dummy source lines 176 c may have a width differentfrom that of the CSL 144.

In example embodiments, at least one dummy source line 176 c may have awidth W3 greater than a width W4 of the CSL 144, and remaining dummysource lines 176 c may have a width substantially the same as the widthW4 of the CSL 144. In some embodiments, the dummy source lines 176 c mayhave a width greater than the width W4 of the CSL 144.

The dummy pattern may include the same material as that of a gate lineon the cell region. In some embodiments, the dummy pattern at a certainlevel may include a conductive pattern formed of the same material asthat of the gate line, and a second sacrificial pattern formed of anitride. The dummy pattern at a certain level may only include theconductive pattern.

The semiconductor device of FIG. 29 may be manufactured by a methodsubstantially the same as or similar to that illustrated with referenceto FIGS. 23 and 24 except that at least a portion of the second openings172 c may be formed to have a different width from a width of the firstopening 122.

FIG. 30 is a top plan view illustrating a semiconductor device inaccordance with example embodiments.

The semiconductor device of FIG. 30 may have elements and/orconstructions substantially the same as or similar to those illustratedwith reference to FIGS. 1 to 4 except for a dummy structure on a dummyregion. Thus, detailed descriptions on repeated elements and/orstructures are omitted herein, and like reference numerals are used todesignate like elements

Referring to FIG. 30, the dummy structure on the dummy region mayinclude second structures 180 a and 180 b having stepped structuresalong the third direction, second and third openings 182 a and 182 bextending through the second structures 180 a and 180 b and first andsecond dummy source lines 186 a and 186 b formed in the second opening182 a and the third opening 182 b, respectively.

The second structures 180 a and 180 b may include insulating interlayerpatterns and dummy patterns that may be alternately stacked.

The second opening 182 a and the third opening 182 b may have differentorientations or different shapes.

In example embodiments, the second opening 182 a may extend in the thirddirection. The third opening 182 b may extend in a fourth directiondiagonal to the second and third directions. Thus, the second structure180 a defined by the second openings 182 a and the second structure 180b defined by the third openings 182 b may also have differentorientations or different shapes.

However, the shapes of the second and third openings 182 a and 182 b maynot be specifically limited, and may be modified in consideration of areduction of stress. In some embodiments, the second and third openings182 a and 182 b may have any shape selected from those of the secondopenings illustrated in the above-described embodiments. The shapes ofthe second structures 180 a and 180 b may be also modified byconstructions of the second and third openings 182 a and 182 b.

The dummy patterns may include substantially the same material as thatof a gate line on a cell region.

The semiconductor device of FIG. 30 may be manufacture by a methodsubstantially the same as or similar to those illustrated with referenceto FIGS. 23 and 24 except that the second and third openings havingvarious shapes may be formed on the dummy region.

FIG. 31 is a top plan view illustrating a semiconductor device inaccordance with example embodiments.

Referring to FIG. 31, the semiconductor device may include a memory cellstructure on a cell region of a substrate 100, and a dummy structure ona dummy region of the substrate 100. A peripheral circuit region(abbreviated as Peri Region in FIG. 31) may be located at an outside ofthe cell region and the dummy region.

A construction on the cell region and the dummy region may be selectedfrom the embodiments as described above, e.g., as illustrated withreference to FIGS. 1 to 4.

Peripheral circuits may be disposed on the peripheral circuit region ofthe substrate 100. An insulating interlayer covering the peripheralcircuits may be formed on the substrate 100. The insulating interlayermay be a portion of the lower insulation layer 108 illustrated in FIGS.2 and 4.

A dummy conductive pattern 190 may be formed through the insulatinginterlayer. The dummy conductive pattern 190 may extend to a top surfaceof the substrate 100. The dummy conductive pattern 190 may be formedtogether with the CSL 144 and a dummy source line 146. Thus, the dummyconductive pattern 190, the CSL 144 and the dummy source line 146 mayinclude the same conductive material.

In example embodiments, the dummy conductive pattern 190 may extend inthe third direction. In some embodiments, the dummy conductive pattern190 may extend in the second direction or the fourth direction.

In example embodiments, widths of the dummy conductive patterns 190 maybe the same or different.

The dummy conductive patterns 190 may have various shapes. In exampleembodiments, the dummy conductive pattern 190 may have any shape of thedummy source lines as described above. A stress imposed on the cellregion may be further reduced by the conductive patterns 190.

In a manufacture of the semiconductor device illustrated in FIG. 31, theperipheral circuits may be formed on the peripheral circuit region ofthe substrate 100. The peripheral circuit may include transistors.

Subsequently, processes substantially the same as or similar to FIGS. 5to 13 may be performed to obtain the semiconductor device of FIG. 31. Inthe processes, a third opening 188 may be formed through the insulatinginterlayer on the peripheral circuit region while forming first andsecond openings 122 and 124. Thus, the dummy conductive pattern 190 maybe formed in the third opening 188 while forming the CSL 144 and thedummy source line 146.

According to example embodiments, a dummy source line may be formed on adummy region. A configuration or a shape of the dummy source line may bedifferent from that of a common source line on a cell region. Thus, astress imposed on the cell region may be dispersed and reduced whileforming the common source line. At least a portion of dummy patterns mayinclude the same conductive material as that included in gate lines.Thus, a nitride from sacrificial patterns may be fully removed or anamount of the nitride may be decreased, so a stress from the nitride maybe also reduced. Therefore, stress-related defects in a semiconductordevice may be suppressed.

In example embodiments, a nonvolatile memory may be embodied to includea three dimensional (3D) memory array. The 3D memory array may bemonolithically formed on a substrate (e.g., semiconductor substrate suchas silicon, or semiconductor-on-insulator substrate). The 3D memoryarray may include two or more physical levels of memory cells having anactive area disposed above the substrate and circuitry associated withthe operation of those memory cells, whether such associated circuitryis above or within such substrate. The layers of each level of the arraymay be directly deposited on the layers of each underlying level of thearray.

In example embodiments, the 3D memory array may include vertical NANDstrings that are vertically oriented such that at least one memory cellis located over another memory cell. The at least one memory cell maycomprise a charge trap layer.

The following patent documents, which are hereby incorporated byreference in their entirety, describe suitable configurations forthree-dimensional memory arrays, in which the three-dimensional memoryarray is configured as a plurality of levels, with word lines and/or bitlines shared between levels: U.S. Pat. Nos. 7,679,133; 8,553,466;8,654,587; 8,559,235; and US Pat. Pub. No. 2011/0233648.

Example embodiments have been disclosed herein, and although specificterms are employed, they are used and are to be interpreted in a genericand descriptive sense only and not for purpose of limitation. In someinstances, as would be apparent to one of ordinary skill in the art asof the filing of the present application, features, characteristics,and/or elements described in connection with a particular embodiment maybe used singly or in combination with features, characteristics, and/orelements described in connection with other embodiments unless otherwisespecifically indicated. Accordingly, it will be understood by those ofskill in the art that various changes in form and details may be madewithout departing from the spirit and scope of the present invention asset forth in the following claims.

What is claimed is:
 1. A semiconductor device, comprising: a substrateincluding a cell region and a dummy region; first channel structures onthe cell region of the substrate, the first channel structures extendingin a first direction vertical with respect to a top surface of thesubstrate; gate lines surrounding outer sidewalls of the first channelstructures and extending in a second direction parallel to the topsurface of the substrate, the gate lines being spaced apart from eachother along the first direction; cutting lines between the gate lines onthe cell region, the cutting lines extending in the second direction;dummy patterns spaced apart from each other along the first direction onthe dummy region, the dummy patterns having a stepped shape along athird direction parallel to the top surface of the substrate andperpendicular to the second direction, at least a portion of the dummypatterns including a same conductive material as that included in thegate lines; and dummy lines extending through the dummy patterns.
 2. Thesemiconductor device as claimed in claim 1, wherein the dummy region isadjacent to an end portion of the cell region in the third direction. 3.The semiconductor device as claimed in claim 1, wherein the dummy linesinclude a same conductive material as that included in the cuttinglines.
 4. The semiconductor device as claimed in claim 1, wherein thedummy lines extend in the third direction.
 5. The semiconductor deviceas claimed in claim 4, wherein a distance between the dummy lines isequal to or greater than a distance between the cutting lines.
 6. Thesemiconductor device as claimed in claim 4, wherein: at least one of thedummy patterns includes conductive patterns spaced apart in the seconddirection, and a sacrificial pattern interposed between the conductivepatterns, and the conductive patterns include a same conductive materialas that of the gate lines, and the sacrificial pattern includes anitride.
 7. The semiconductor device as claimed in claim 1, wherein thedummy lines extend in a fourth direction diagonal to the seconddirection.
 8. The semiconductor device as claimed in claim 1, whereinthe dummy lines extend in the second direction.
 9. The semiconductordevice as claimed in claim 8, wherein a first portion of the dummypatterns includes a same conductive material as that of the gate lines,and a second portion of the dummy patterns different than the firstportion includes a conductive pattern and a sacrificial pattern, theconductive pattern including the conductive material and the sacrificialpattern including a nitride.
 10. The semiconductor device as claimed inclaim 1, wherein the dummy patterns are positioned at correspondinglevels of the gate lines.
 11. The semiconductor device as claimed inclaim 1, further comprising insulating interlayer patterns between thedummy patterns neighboring in the first direction and between the gatelines neighboring in the first direction.
 12. The semiconductor deviceas claimed in claim 1, wherein the cutting lines serve as common sourcelines, and the dummy lines serve as dummy source lines.
 13. Thesemiconductor device as claimed in claim 1, further comprising a thirdchannel structure extending through the dummy patterns on the dummyregion of the substrate.
 14. The semiconductor device as claimed inclaim 1 further comprising a dummy cell on a portion of the cell regionadjacent to the dummy region.
 15. A semiconductor device, comprising: asubstrate including a cell region and a dummy region; first channelstructures on the cell region of the substrate, the first channelstructures extending in a first direction vertical with respect to a topsurface of the substrate; gate lines surrounding outer sidewalls of thefirst channel structures and extending in a second direction parallel tothe top surface of the substrate, the gate lines being spaced apart fromeach other along the first direction; first insulating interlayerpatterns between gate lines neighboring to each other in the firstdirection; cutting lines interposed between the gate lines on the cellregion, the cutting lines extending in the second direction; dummypatterns spaced apart from each other along the first direction on thedummy region, the dummy patterns having a stepped shape along a thirddirection parallel to the top surface of the substrate and perpendicularto the second direction, at least a portion of the dummy patternsincluding a same conductive material as that included in the gate lines;second insulating interlayer patterns between dummy patterns neighboringeach other in the first direction; and dummy lines extending through thedummy patterns and the second insulating interlayer patterns.
 16. Asemiconductor device, comprising: a substrate including a cell regionand a dummy region; first channel structures on the cell region of thesubstrate, the first channel structures extending in a first directionvertical with respect to a top surface of the substrate; gate linessurrounding outer sidewalls of the first channel structures andextending in a second direction parallel to the top surface of thesubstrate, the gate lines being spaced apart from each other along thefirst direction; common source lines between the gate lines on the cellregion, the common source lines extending in the second direction; dummypatterns spaced apart from each other along the first direction on thedummy region, the dummy patterns having a stepped shape along a thirddirection parallel to the top surface of the substrate and perpendicularto the second direction, at least a portion of the dummy patternsincluding a same conductive material as that included in the gate lines;and dummy source lines extending through the dummy patterns, the dummysource lines having a different configuration than the common sourcelines in top view.
 17. The semiconductor device as claimed in claim 16,wherein the dummy source lines extend in a different direction than thecommon source lines, as viewed in top view.
 18. The semiconductor deviceas claimed in claim 17, wherein a distance between neighboring dummysource lines is greater than a distance between neighboring commonsource lines.
 19. The semiconductor device as claimed in claim 17,wherein the dummy source lines and the common source lines includes asame conductive material.
 20. The semiconductor device as claimed inclaim 16, wherein the dummy source lines includes a plurality of dummysource line segments spaced apart from each other in the second andthird directions.